Image Processing, FPGA, Real-Time, Low-Power, Hardware
We are now trying to implement state-of-the art image processing algorithms onto FPGA for mobile and robot applications, where real-time, low-power implementation is required. We are also working on hardware architecture design and algorithm optimization/reconsideration for efficient processing. In addition, we would like to make all the source files such as Verilog codes and schematics of the boards as open source so that anyone can use and contribute to them.
|Contact||Toshihiko Yamasaki（Department of Information and Communication Engineering, Graduate School of Information Science and Technology）|
|References||1. Y. Yamanaka, T. Yamasaki, K. Aizawa, “Histogram of Oriented Gradients algorithm for hardware implementation,” 72nd National Convention of IPSJ, 2Y-7, pp. 2-663-2-664, March 9-11, 2010. (in Japanese)|