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Ultra high-capacity semiconductor memory system

Devices and Materials


semiconductor、LSI、memory、circuit design、SSD (Solid-State Drive)

High capacity semiconductor memory has been creating new portable applications such as mobile phones, MP3 players and digital cameras. By further increasing the memory capacity by two orders of magnitudes, $10 PC can be realized, which will enable children in world’s poorest countries to access a high-level education through an internet. Since Gordon Moore advocated the "Moore's law" in 1965, under which the number of transistors in a chip doubles every 18 months, the capacity and performance of LSIs have been improving drastically by scaling transistors. However, in 2015, when the transistor size is as small as 10nm, it is predicted that the Moore's law will face a serious scaling limit because of the quantum mechanical effect and statistical fluctuation. On the other hand, as the data traffic through an internet drastically increases, power consumption at data centers of IT service providers such as Google and has drastically increased. During the last five years, power consumption at data centers in the U.S. doubled, which correspond to building 5 nuclear plants and is causing serious environmental problems. To overcome this problem, Takeuchi Lab. is developing low-power high-capacity semiconductor memory technologies such as a SSD (Solid-State Drive) with 3D-integrated LSIs and Fe (Ferroelectric)-NAND flash memories with ferroelectric gate dielectric. For more detailed information, please see at

Research field of Takeuchi Lab.

Research field of Takeuchi Lab.

Contact Ken Takeuchi(Department of Electrical Engineering and Information Systems, Graduate School of Engineering)
References [1] Ken Takeuchi, “NAND successful as a media for SSD,” IEEE International Solid-State Circuits Conference (ISSCC), Tutorial-T7, February 2008.
[2] Ken Takeuchi, “Novel Co-design of NAND Flash Memory and NAND Flash Controller Circuits for sub-30nm Low-Power High-Speed Solid-State Drives (SSD),” IEEE Symp. on VLSI Circuits, pp.124-125, June 2008.
[3] Shigeki Sakai, et. al., “Highly Scalable Fe(Ferroelectric)-NAND Cell with MFIS (Metal-Ferroelectric-Insulator-Semiconductor) Structure for Sub-10nm Tera-Bit Capacity NAND Flash Memories,” IEEE Non-volatile Semiconductor Memory Workshop (NVSMW), pp.103-104, May 2008.
[4] Koichi Ishida, et. al., “A 1.8V 30nJ Adaptive Program-Voltage (20V) Generator for 3D-Integrated NAND Flash SSD”, IEEE International Solid-State Circuits Conference (ISSCC), February 2009.
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